1. Field of the Invention
The present invention relates generally to a method of fabricating a power device. More particularly, the present invention relates to a power device with low parasitic transistor and a fabrication method thereof.
2. Description of the Prior Art
A power device is mainly used in power management, for instance, being applied in a switching power supply, a management integrated circuit in the core or a peripheral region of computer, a backlight power supply, and in an electric motor control. The type of the power devices described above include an insulated gate bipolar transistor (IGBT), a metal-oxide-semiconductor field effect transistor (MOSFET), and a bipolar junction transistor (BJT), among which the MOSFET is widely applied in various domains because of its energy saving properties and ability to provide faster switch speed.
It has been the trend to scale down the sizes of integrated circuit devices to increase the integration level and density. However, as the distance between devices is decreased, parasitic transistors form more easily within semiconductor regions with different conductive types. In addition, as the sizes of devices are decreased, the distance between source doped region and drain doped region is shortened, leading to the decrease of breakdown voltage and the occurrence of current leaking.
Therefore, it is necessary to invent a novel structure and a fabrication method of a power device to solve the problems such as breakdown voltage, current leaking, and parasitic transistors in a convenient and economical way.